說明

• NB3L208KMNGEVB, Evaluation Board is designed to test and evaluate the NB3L208K which is a differential 1:8 Clock fan-out buffer with High-speed Current Steering Logic (HCSL) outputs. Inputs can directly accept differential LVPECL, LVDS and HCSL signals. Single-ended LVPECL, HCSL, LVCMOS, or LVTTL levels are accepted with a proper external VTH reference supply. These signals will be translated to HCSL and eight identical copies of Clock will be distributed, operating up to 350 MHz